High performance analog charge pumped phase locked loop (PLL) architecture with process and temperature compensation in closed loop bandwidth

摘要

The present invention achieves technical advantages as a high performance analog charge pumped phase locked loop (PLL)( 10 ) with process and temperature compensation in closed loop bandwidth. The PLL reduces the variation in bandwidth and stability by making the product K_VCO*I_CP independent of process and temperature variation. The PLL achieves a higher performance than existing PLL architectures, achieving a high dynamic range up to at least 110 dB, such that a PWM class-D amplifier is realizable with this PLL. The PLL has a constant bandwidth and damping factor while using an analog charge pump ( 16 ).