发明名称 |
Design implementation to suppress latchup in voltage tolerant circuits |
摘要 |
The voltage tolerant circuit with improved latchup suppression includes: a diode device having a first end coupled to a source voltage node; a first NWELL guard ring surrounding the diode device; a diode coupled between a second end of the string of diodes and an output pad; a second NWELL guard ring surrounding the diode; and a transistor device coupled between the output pad and a substrate node. The NWELL guardrings disrupt the parasitic SCR operation by adding an additional N+ diffusion without affecting the substrate pump current delivered by the diode.
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申请公布号 |
US7167350(B2) |
申请公布日期 |
2007.01.23 |
申请号 |
US20040982347 |
申请日期 |
2004.11.03 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
SALCEDO-SUNER JORGE;DUVVURY CHARVAKA;CLINE ROGER A.;CADENA-HERNANDEZ JOSE A. |
分类号 |
H02H9/00;H01L23/62;H01L27/02;H01L27/092;H01L29/72 |
主分类号 |
H02H9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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