发明名称 Apparatus and method for reducing test resources in testing DRAMs
摘要 An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.
申请公布号 US7168018(B2) 申请公布日期 2007.01.23
申请号 US20040853573 申请日期 2004.05.25
申请人 发明人
分类号 G11C29/00;G01R31/02;G11C29/26;G11C29/40;G11C29/48 主分类号 G11C29/00
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