| 摘要 |
A semiconductor IC(Integrated Circuit) device and a manufacturing method thereof are provided to improve resistive capability against soft errors by increasing storage node capacity of a memory cell. A memory cell is formed within a memory cell forming region of a semiconductor substrate. The memory cell includes a first N channel MISFET(Metal Insulator Semiconductor Field Effect Transistor), a second N channel MISFET, a first P channel MISFET, and a second P channel MISFET. Each MISFET is composed of a gate electrode, and source/drain regions in the substrate. The gate electrodes of the first N and P channel MISFETs are formed as one piece by using a first common gate electrode(11a). The gate electrode of the second N and P channel MISFETs are formed as one piece by using a second common gate electrode(11b). A silicon nitride layer is formed on the resultant structure. The silicon nitride layer includes first and second opening portions for exposing selectively the first and second common gate electrodes and drain regions to the outside. First and second conductive layers are filled in the first and second opening portions, respectively. |
