| 摘要 |
A scan read block having the same circuit structure of scan latch and bit cells is provided to reduce the layout area by applying a unit bit cell structure to a scan latch circuit, and to increase a noise margin by copying data of bit cells through bit lines and inverse bit lines. A bit cell array(810) includes a plurality of bit cells, which input and output data through a corresponding bit line and a corresponding inverse bit line in response to a corresponding word line scan signal. A scan latch block(820) includes a plurality of scan latch circuits, which copy the data stored in corresponding bit cells through the bit lines and the inverse bit lines in response to scan latch signals. The data of the bit cell array are copied to the corresponding latch circuit while both the word line scan signals and the scan latch signals are in the enable states.
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