发明名称 |
PROGRAMMABLE HARDWARE FOR DEEP PACKET FILTERING |
摘要 |
An improved deep packet filter system designed to optimize search of dynamic patterns for a high speed network traffic. The improved deep packet filter system is a hardware-based system with optimized logic area. One optimization technique is the sharing of common sub-logic in the hardware design to reduce the number of gates that are required. Another optimization technique is the use of a built-in memory to store portions of the pattern set, also resulting in a reduction of gates. The reduction of the logic area allows the deep packet filter system to be implemented onto a single field-programmable array chip. ® KIPO & WIPO 2007
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申请公布号 |
KR20070010064(A) |
申请公布日期 |
2007.01.19 |
申请号 |
KR20067024324 |
申请日期 |
2006.11.20 |
申请人 |
THE REGENTS OF THE UNIVERSITY OF CALIFORNIA |
发明人 |
CHO, YOUNG H.;MANGIONE SMITH WILLIAM H. |
分类号 |
H04L12/28;H04L12/02 |
主分类号 |
H04L12/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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