发明名称 Synthesis approach for active leakage power reduction using dynamic supply gating
摘要 A logic synthesis method to apply supply gating to idle portions of general logic circuits in their active mode of operation to reduce power requirements and the circuits resulting therefrom. A Shannon expansion is utilized to determine idle portions and active portions of the general logic circuits.
申请公布号 US2007016808(A1) 申请公布日期 2007.01.18
申请号 US20060450711 申请日期 2006.06.09
申请人 BHUNIA SWARUP;BANERJEE NILANJAN;MAHMOODI HAMID;CHEN QIKAI;ROY KAUSHIK 发明人 BHUNIA SWARUP;BANERJEE NILANJAN;MAHMOODI HAMID;CHEN QIKAI;ROY KAUSHIK
分类号 G06F1/00;G06F1/26;G06F1/32 主分类号 G06F1/00
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