发明名称 |
Reduced bus turnaround time in a multiprocessor architecture |
摘要 |
Systems and methods of reducing bus turnaround time in a multiprocessor architecture are disclosed. An exemplary method may include mastering the system bus within one idle bus clock cycle of a bus handoff. The method may also include bypassing data from recovery latches and instead receiving data from pipeline latches into core logic, the received data mirroring data driven onto the system bus
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申请公布号 |
US2007016706(A1) |
申请公布日期 |
2007.01.18 |
申请号 |
US20050182378 |
申请日期 |
2005.07.15 |
申请人 |
ARNOLD BARRY;GRIFFITH MIKE |
发明人 |
ARNOLD BARRY;GRIFFITH MIKE |
分类号 |
G06F13/00 |
主分类号 |
G06F13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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