POWER FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF

摘要

Method for manufacturing a vertical power MOS transistor on a wide band gap semiconductor substrate (10) comprising a superficial semiconductor layer (11), the method comprising the steps of: forming a screening structure (12) on the superficial semiconductor layer (11) comprising at least one dielectric layer (12) carrying out at least a first ion implantation of a first type of dopant for forming at least one deep implanted region (14a); carrying out at least a second ion implantation of the first type of dopant for forming at least one body region (16) of the MOS transistor aligned with the deep implanted region (14a); the method comprising an activation thermal process with 1-14 low thermal budget of the first type and second type of dopant suitable to complete said formation of the body region (16), and of the deep implanted region (14a).