发明名称 CIRCUIT AND METHOD OF TRACK AND HOLD
摘要 A track and hold circuit and a track and hold method are provided to prevent distortion of a sampled signal, and to reduce a variation of a channel charge injection and a channel conductance. In a track and hold circuit, a first level shifter generates a first signal. A first MOS(Metal Oxide Semi-conductor) transistor provides an output stage with a sampled signal, and samples the first signal in response to a clock signal. A hold capacitor is coupled to the output stage to maintain the sampled signal. A second level shifter performs a level shift of an analog input signal as a direct voltage having a second level, and provides a gate of the first MOS transistor with the analog input signal.
申请公布号 KR20070008998(A) 申请公布日期 2007.01.18
申请号 KR20050063902 申请日期 2005.07.14
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 LIM, SUNG SANG
分类号 H03M1/54 主分类号 H03M1/54
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