Duplicated double checking production rule set for fault-tolerant electronics

摘要

Systems and methods for mitigating the effects of soft errors in asynchronous digital circuits. Circuits are constructed using stages comprising doubled logic elements which are connected to c-elements that compare the output states of the double logic elements. The inputs of logic elements in a stage are inhibited from changing until the outputs of the c-elements of that stage are enabled. The c-elements inhibit the propagation of a soft error by halting the operation of the circuit until the temporary effects of the soft error pass.