High-density logic techniques with reduced-stack multi-gate field effect transistors

摘要

Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or "stacked" portions of logic gates. Circuit area can be reduced and performance can be enhanced.