发明名称 Sample-and-hold circuits having reduced channel conductance variation and methods of operation thereof
摘要 An electronic device, such as a sample-and-hold circuit, includes a field effect transistor (FET), a capacitor, and a voltage offset circuit. The FET is configured to receive a signal at a first terminal thereof and selectively provide the signal to a second terminal thereof responsive to a switching signal at a gate terminal thereof. The capacitor is electrically connected to the second terminal of the FET. The voltage offset circuit is electrically connected to the first terminal and the gate terminal of the FET. The voltage offset circuit is configured to maintain a substantially constant voltage differential between the first terminal and the gate terminal of the FET while the signal is provided to the second terminal of the FET and substantially independent of a voltage level of an input signal. Related methods of operation are also discussed.
申请公布号 US2007013417(A1) 申请公布日期 2007.01.18
申请号 US20060443730 申请日期 2006.05.31
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 LIM SUNG-SANG
分类号 G11C27/02 主分类号 G11C27/02
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