发明名称 |
Memory controller interface for micro-tiled memory access |
摘要 |
In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.
|
申请公布号 |
US2007013704(A1) |
申请公布日期 |
2007.01.18 |
申请号 |
US20050173375 |
申请日期 |
2005.06.30 |
申请人 |
MACWILLIAMS PETER;AKIYAMA JAMES;GABEL DOUGLAS |
发明人 |
MACWILLIAMS PETER;AKIYAMA JAMES;GABEL DOUGLAS |
分类号 |
G06F15/167;G06F12/00;G06F13/00;G06F13/28 |
主分类号 |
G06F15/167 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|