| 摘要 |
The memory cell comprises first and second circuit inverters (Tp1 , Tn1 ; Tp2, Tn2), connected in a loop. First and second decoupling transistors (Tpd, Tnd), normally locked outside writing phases, are respectively connected between an output (Q) from the second inverter circuit and first and second inputs (A1, A2) to the first inverter circuit. The memory cell is thus protected against transitory perturbations caused by ionising particles. The gates of the decoupling transistors are preferably respectively connected to a supply voltage (Vdd) for the type P decoupling transistors and to ground for type N decoupling transistors. |
