| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a more suitable cash device and arithmetic unit capable of variably controlling a hit rate to a cache with the least impairment of rapidity of a cache memory even when the same data is frequently accessed. <P>SOLUTION: A cache controller 4 is connected between a processor 1 and a main memory 2. The cache controller 4 is connected to the cache memory 3 capable of reading and writing at higher speed than a main memory 2. The cache memory 3 has a plurality of cache lines 14 each comprising a tag section 11 showing an address on the main memory 2, a capacity section 12 holding a capacity value of a cache block 13, and the cache block 13. When there is a read request to the main memory 2 from the processor 1, the cache controller 4 examines whether the cache memory 3 has the requested contents. A cache capacity determining part 22 determines the capacity value of the cache block 13 and provides it to the capacity section 12. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
