发明名称 TRANSISTOR MODEL GENERATION DEVICE AND TRANSISTOR MODEL GENERATION METHOD
摘要 PROBLEM TO BE SOLVED: To provide a transistor model generation device and a transistor model generation method, easily creating a transistor model reflecting a diffusion layer length-dependent parameter corresponding to each diffusion layer. SOLUTION: A transistor extraction processing part extracts a transistor having a gate area overlapping a non-rectangular diffusion layer area from mask layout data. A rectangle division processing part sets a dividing line in a gate length direction of the transistor to divide the non-rectangular area into a plurality of rectangular areas. A mask layout data association processing part associates the non-rectangular diffusion layer area and the plurality of rectangular diffusion layer areas to the mask layout data. A size calculation processing part calculates size information showing a size of each of the plurality of divided rectangular areas. A correction value calculation processing part calculates the diffusion layer length-dependent parameter of each of the plurality of rectangular areas. A transistor model registration part registers the transistor model on the basis of the diffusion layer length-dependent parameter. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007011995(A) 申请公布日期 2007.01.18
申请号 JP20050195485 申请日期 2005.07.04
申请人 NEC ELECTRONICS CORP 发明人 MIYAGAWA SEIJI
分类号 G06F17/50;H01L21/336;H01L21/82;H01L21/822;H01L21/8234;H01L27/04;H01L27/088;H01L29/78 主分类号 G06F17/50
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