发明名称 Arithmetic apparatus and arithmetic method
摘要 <p>An arithmetic apparatus and an arithmetic method capable of executing arithmetic by reconfigurable hardware, shortening a processing time of arithmetic including conditional branches causing a heavy processing load and improving a processing speed even when conditional branches exist in a loop of performing repeating arithmetic processing, wherein arithmetic processing including conditional branches is divided to first processing of unconditional branches and second processing with conditional branches, the first processing of unconditional branches is assigned to reconfigurable arithmetic means, configuration information of hardware is generated based on the first processing, the first processing is executed by the reconfigured arithmetic means based on the configuration information, the second processing with conditional branches is assigned to a CPU or other arithmetic means, the assigned second processing with conditional branches is executed by the CPU, and a result of the processing is used for correcting a result of said first processing, so that a result of arithmetic processing including conditional branches is obtained. </p>
申请公布号 EP1391829(A3) 申请公布日期 2007.01.17
申请号 EP20030291947 申请日期 2003.08.01
申请人 SONY CORPORATION 发明人 UCHINO, MANABU
分类号 G06F15/78;G06F7/00;G06F9/32;G06F9/38;G06F9/45;G06F11/00 主分类号 G06F15/78
代理机构 代理人
主权项
地址