| 摘要 |
A semiconductor memory device is provided to secure operational stability at a high-speed operation by resetting a pipe latch unit only in a writing operation. A pipe latch unit(400) receives data. An input control unit(200) controls the timing of inputting the data received through a data line to the pipe latch unit. An output control unit(300) controls the output timing of the data stored in the pipe latch unit. A reset control unit(100) resets the input control unit and the output control unit in a writing operation. The reset control unit activates a reset control signal when one of a power-up signal, a clock enable signal, and a write/read flag signal is in an inactive state.
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