| 摘要 |
A CMOS device is provided to improve integration by including a stacked structure in which an n-MOS transistor and a p-MOS transistor are vertically stacked. An n-type transistor is formed on a silicon substrate(30) whose upper surface is (100). The silicon substrate is a part of an SOI substrate. The n-type transistor is covered with an interlayer dielectric(40). A p-type transistor is formed on the interlayer dielectric. The channel of the n-type transistor is , and the channel of the p-type transistor is . The p-type transistor can be a p-MOS FET or a p-MOS FinFET(T2).
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