SEMICONDUCTOR MEMORY DEVICE HAVING COMMAND DELAY CIRCUIT

摘要

A semiconductor memory device having a command delay circuit is provided to test and screen an AC parameter of the semiconductor device having small margin of the AC parameter in case of a test apparatus for a low frequency product, by delaying an active command signal in a normal path internal clock. In a semiconductor memory device, a delay command circuit delays an active command signal in a normal path internal clock, which is generated by a clock signal in a test apparatus for AC parameter test of the semiconductor memory device and used as an internal clock. The AC parameter is a time from the input of the active command signal to the input of a read command signal into the semiconductor device. The command delay circuit comprises a normal path part for generating the normal path internal clock in response to the clock signal of the test apparatus, and a delay path part for delaying the active command signal of the normal path internal clock.