发明名称 |
Manufacturing method for semiconductor device |
摘要 |
With respect to the selective ratio in the etching process, it is an object to give design freedom in size of an LDD overlapped with a gate electrode, which is formed in a self-aligning manner, by performing an etching process under an etching condition that has a high selective ratio between a mask pattern and metal such as titanium in forming a first conductive layer pattern. A laminated structure comprising a lower first conductive layer and an upper second conductive layer is formed over a semiconductor layer with a gate insulating film interposed therebetween, a mask pattern is formed on the laminated structure, a condition that an etching rate of the mask pattern is fast is used and the second conductive layer and the first conductive layer are etched to form a tapered first conductive layer pattern, and the second conductive layer in the first conductive layer pattern is selectively etched in accordance with the left mask pattern to form a second conductive layer pattern in which a width of the first conductive layer is longer than that of the second conductive layer.
|
申请公布号 |
US7163852(B2) |
申请公布日期 |
2007.01.16 |
申请号 |
US20030731000 |
申请日期 |
2003.12.10 |
申请人 |
SEMICONDUCTOR ENERGY LABORATORY CO., LTD. |
发明人 |
MONOE SHIGEHARU;YOKOSHIMA TAKASHI;SASAGAWA SHINYA |
分类号 |
G02F1/1368;H01L21/84;H01L21/28;H01L21/3065;H01L21/3213;H01L21/336;H01L29/423;H01L29/49;H01L29/786 |
主分类号 |
G02F1/1368 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|