| 摘要 |
In a memory control apparatus for controlling a synchronous memory unit, the apparatus receives a source clock signal, switches ON and OFF the source clock signal in accordance with an access request signal to the synchronous memory unit and an idle state with no access request signal, and transmits the switched ON/OFF source clock signal to the synchronous memory unit, so that the switched ON/OFF source clock signal serves as an internal clock signal within the synchronous memory unit.
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