| 摘要 |
<p>In a delay circuit, when a first conductivity-type transistor (M 6 ) becomes conductive on the basis of one level of its input signal, a first current path is formed through a source side transistor (M 4 ), the first conductivity-type transistor (M 6 ), and a second drive transistor (M 9 ) between a source power line and a sink power line, and its output signal being the delayed inverse of the one level of the input signal is output from a connection point of another source side transistor (M 5 ) and a sink side transistor (M 11 ), and when a second conductivity-type transistor (M 7 ) becomes conductive on the basis of the other level of the input signal, a second current path is formed through a first drive transistor (M 3 ), the second conductivity-type transistor (M 7 ), and another sink side transistor (M 10 ), and the output signal being the delayed inverse of the other level of the input signal is output from the connection point.</p> |
