| 摘要 |
A semiconductor process and apparatus includes forming a floating gate stack structure ( 1 ) and a low voltage transistor gate stack structure ( 2 ) over a substrate ( 11 ) by including a shallow extension implant region ( 51, 52 ) that is aligned with the floating gate ( 13 ). By using a spacer etch process after a deep dielectric isolation (DDI) oxidation step is used to isolate the floating gate ( 13 ), a sub-zero spacer ( 31, 32 ) may be formed for the shallow extension implant ( 41, 42 ) which is subsequently diffused to overlap with the floating gate ( 13 ).
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