| 摘要 |
A sigma-delta converter has a signal input for receiving a data word. A clock signal input is designed to supply a clock signal. The sigma-delta converter includes a first clocked-operation accumulator stage whose input side is connected to the signal input, and at least one second clocked-operation accumulator stage connected in series with the first accumulator stage, with its input side coupled to an accumulator output of the first accumulator stage. The sigma-delta converter is configured to process the data word upon each clock signal only in one accumulator stage in the first and the at least one second accumulator stage, and output the processed data word at the accumulator output of the one accumulator stage. As a result, a time-critical response during signal processing is limited just to the accumulator stage which is currently processing the data word.
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