发明名称 EVALUATION CIRCUIT FOR SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide an evaluation circuit for a semiconductor device capable of measuring precisely a drain current and a gate source/drain capacity sum, in the same measuring object. SOLUTION: A selector circuit 51 determines the first/second selection condition under control of a control signal S50, and selects one out of an S-pad 35 and a node N1 to be connected electrically to a source terminal NS of a measuring objective NMOS transistor MT. A selector circuit 52 determines the first/second selection condition under the control of the control signal S50, and selects one out of a D-pad 31 and the node N1 to be connected electrically to a drain terminal ND of the measuring objective NMOS transistor MT. A selector circuit 53 determines the first/second selection condition under the control of the control signal S50, and selects one out of a B-pad 39 and a node N2 to be connected electrically to a backgate terminal NB of the measuring objective NMOS transistor MT. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007003378(A) 申请公布日期 2007.01.11
申请号 JP20050184578 申请日期 2005.06.24
申请人 RENESAS TECHNOLOGY CORP 发明人 OKAGAKI TAKESHI
分类号 G01R31/26;H01L21/822;H01L27/04 主分类号 G01R31/26
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