| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a phase locked loop and method in which various high-frequency clock signals can be generated even when a power supply voltage level becomes low. <P>SOLUTION: A phase locked loop circuit may include a phase detector receiving an external clock signal and a feedback clock signal and outputting an up signal when a phase of the external clock signal leads a phase of the feedback clock signal and outputting a down signal when the phase of the external clock signal lags the phase of the feedback clock signal, a loop filter circuit increasing a control voltage in response to the up signal and decreasing the control voltage in response to the down signal, and a voltage controlled oscillator circuit receiving the control voltage and directly generating at least n (where n is an integer≥4) internal clock signals. The phase locked loop circuit may also include a voltage controlled oscillator circuit, including at least four loops, receiving the control voltage and generating multiple internal clock signals. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
