| 摘要 |
PROBLEM TO BE SOLVED: To identify, from a top layer, a portion to be analyzed and directly perform cross-sectional analysis without surfacing, a layer including the portion to be analyzed in a semiconductor integrated circuit device by exfoliation and polishing. SOLUTION: The circuit device includes a first analysis mark pattern 12 which is formed on a first wiring layer disposed above a portion 11 to be analyzed, and a second analysis mark pattern 13 which is formed on a second wiring layer disposed above the first wiring layer. In plan view, each of the first and second analysis mark patterns has one side drawn as a straight line in parallel with a straight line passing a point to be analyzed in the portion to be analyzed. Further, the first and second analysis mark patterns overlap the portion to be analyzed such that at least one side of the first and second analysis mark patterns overlaps the portion to be analyzed. In plan view, the first and second analysis mark patterns are stretched and formed to an area not overlapping the portion to be analyzed, in opposite directions with respect to the portion to be analyzed. COPYRIGHT: (C)2007,JPO&INPIT
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