发明名称 Semiconductor integrated circuit verifying and inspecting method
摘要 A method of verifying a semiconductor integrated circuit according to the invention does not compare expected values based on a strobe every cycle but executes a verification on the basis of a signal transition (change) point. At the same time, the verifying method is intended for verifying a path in a circuit through which a signal transition (change) in a result to be output is sent, and can find the drawbacks of a circuit and a pattern in a more upstream process for a design with higher precision as compared with the conventional art so that quality of a design can be enhanced. By using information about the path through which the signal transition is output to carry out an inspection, moreover, it is possible to finally inspect (test) an LSI with high precision and quality.
申请公布号 US2007011506(A1) 申请公布日期 2007.01.11
申请号 US20060480411 申请日期 2006.07.05
申请人 YOSHIDA TAKAKI 发明人 YOSHIDA TAKAKI
分类号 G01R31/28 主分类号 G01R31/28
代理机构 代理人
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