发明名称 |
SELF-SYNCHRONISING BIT ERROR ANALYSER AND CIRCUIT |
摘要 |
A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator compares the first data set with a second data set generated by the receiver LFSR and adjusts the receiver LFSR until the second data set is substantially the same as the first data set.
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申请公布号 |
US2007011534(A1) |
申请公布日期 |
2007.01.11 |
申请号 |
US20050164690 |
申请日期 |
2005.12.01 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BOUDON GERARD;MALCAVET DIDIER;PEREIRA DAVID;STEIMLE ANDRE |
分类号 |
G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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