MULTIPROCESSOR DEVICE AND MEMORY ACCESS METHOD THEREFOR

摘要

PROBLEM TO BE SOLVED: To accurately specify a failure occurrence part even when a plurality of command errors simultaneously occur during a response waiting time of one memory access.

SOLUTION: A processor has a lapsed time clocking part 2a outputting a time-out signal when the processor does not receive a response signal even when a preset prescribed time-out time lapses after transmitting an access signal to a main storage memory 7. A directory control part 9B has a cache access generation information reply part 9c returning the effect of generation of access to a cache memory to the processor of an access source when the access to the cache memory is generated in the main storage memory receiving the access. The processor of the access source has a time-out time resetting part 2b resetting the time-out time preset in the lapsed time clocking part 2a when receiving notification from the cache access generation information reply part 9c.

COPYRIGHT: (C)2007,JPO&INPIT