| 摘要 |
A system and method for internal error checking a semiconductor memory device in a much more area and energy efficient manner. According to the method, a predefined data pattern is written to a plurality of memory cells in the memory device. A pause or waiting time interval is initiated after the predefined data pattern is written to the plurality of memory cells. The time interval is based on temperature conditions of the memory device. After the time interval expires, the contents are read from the plurality of memory cells and a parity check operation is performed on said contents to detect any single bit error based on the predefined data pattern written to the plurality of memory cells. The circuitry required for this error checking technique is minimal, and comprises a register, a parity check circuit and a control circuit.
|
