发明名称 RECEPTION DATA STORAGE CIRCUIT
摘要 PROBLEM TO BE SOLVED: To suppress influences upon signal processing to a minimum by automatically recovering trouble in a reception data storage section comprising a plurality of SRAMs. SOLUTION: A memory supervisory and control section 31 monitors currents supplied from a power source section 40 to SRAMs 11-13 using current detection sections 21-23. If an SRAM to which an abnormal current flows is detected, a bus connected to the relevant SRAM is temporarily made into high impedance and disconnected in a disable state, and a power source supplying said current is turned off. After the lapse of a fixed time, the relevant SRAM is reset into enable state, and power supply is started again. The current detection sections monitor the operating current of the relevant SRAM and if it is a normal state for a fixed time, the bus connected to the relevant SRAM is connected again. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007006336(A) 申请公布日期 2007.01.11
申请号 JP20050186502 申请日期 2005.06.27
申请人 NEC CORP 发明人 TAKAYANAGI YOSHIO;YATAGAI TETSUYA;OWADA HIDEKI;SOMA SHINTARO;NAKANO TATSUYA;HOSHINA KOJI
分类号 H04B7/26 主分类号 H04B7/26
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