| 摘要 |
A Reed Solomon decoder architecture. The architecture uses a modified version of the error-evaluator polynomial form proposed by Horiguchi, and later improved by Feng. The architecture is an improvement over Feng in that the area of the dominant PDU unit has been significantly reduced, while maintaining nearly the same iteration time, in novel slice circuitry which rotates terms to share a common multiplier and other circuitry. In addition, a novel implementation of storage of the B polynomial and associated overflow flags allows its storage to be minimized and provides equivalent functioning of the Chien search unit using a proprietary dual-multiplier arrangement in place of random multipliers used by Feng.
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