| 摘要 |
A microprocessor interface system including a system bus with a bus clock and a quad-pumped address signal group, and including multiple devices coupled to the system bus. Each device is configured to perform a quad-pumped transaction on the system bus in which multiple request packets are sequentially transferred via the address signal group during each of multiple phases of one cycle of the bus clock. The devices may include at least one microprocessor and one or more bus agents. In one embodiment, the first address data is multiplexed onto the address signal group during first and second request packets during a first phase of the bus clock cycle, and the second address data is multiplexed onto the address signal group during third and fourth request packets during a second phase of the bus clock cycle.
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