METHOD AND APPARATUS FOR CO-VERIFICATION OF DIGITAL DESIGNS

摘要

A method and apparatus for development and concurrent verification of digital designs including a combination of a microprocessor (22) and discrete logic design blocks (17, 18). The hardware/software design development and co-verification processing of digital designs is accelerated by placing the microprocessor in an FPGA device and logic circuits in an HDL simulator (33). The microprocessor and logic circuits are connected via a common bus (21) and synchronization of both environments is achieved by using a simulator clock exclusively when both microprocessor and logic simulator need to communicate with each other. The system and method of the present invention provides a unique arrangement of a processor clocking scheme. An essential part of the invention is a clock switch (7) responsive to the areas of RAM a processor is addressing and accordingly switching a clock signal to the processor from either a hardware clock generator (8) or a software simulator (33).