发明名称 Switching arrangement for computer, has IO warrior connected with controllers of graphic display by decoder logic that is parallel port output module, which generates two output signals to graphic display
摘要 <p>The arrangement has an IO warrior (2) connected with controllers of a graphic display (1) by a decoder logic (3), where the decoder logic is a parallel port output module, which generates two output signals (CS1, CS2) to the graphic display under utilization of I2> C-busses. The decoder logic has a parallel circuit of one AND gate with another two AND gates, where two output signals of the former AND gate and one of the two AND gates are the output signals of the graphic display.</p>
申请公布号 DE102005032108(A1) 申请公布日期 2007.01.11
申请号 DE20051032108 申请日期 2005.07.07
申请人 REPPIN, MICHAEL 发明人 REPPIN, MICHAEL
分类号 G06F13/00;G09F9/00 主分类号 G06F13/00
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