摘要 |
<p>The arrangement has an IO warrior (2) connected with controllers of a graphic display (1) by a decoder logic (3), where the decoder logic is a parallel port output module, which generates two output signals (CS1, CS2) to the graphic display under utilization of I2> C-busses. The decoder logic has a parallel circuit of one AND gate with another two AND gates, where two output signals of the former AND gate and one of the two AND gates are the output signals of the graphic display.</p> |