发明名称 |
CLEARANCE HOLE SIZE ADJUSTMENT FOR IMPEDANCE CONTROL IN MULTILAYER ELECTRONIC PACKAGING AND PRINTED CIRCUIT BOARDS |
摘要 |
The present invention provides a technique for adjusting the size of clearance holes for impedance control in multilayer electronic packaging and printed circuit boards. The method comprises: providing parameters for a structure having a clearance hole and at least one via passing through the clearance hole; calculating a characteristic impedance for the at least one via; and adjusting at least a size of the clearance hole until the characteristic impedance for the at least one via is approximately equal to a desired characteristic impedance.
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申请公布号 |
US2007008049(A1) |
申请公布日期 |
2007.01.11 |
申请号 |
US20050160785 |
申请日期 |
2005.07.08 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
DYCKMAN WARREN D.;LAFONTANT GARY;PILLAI EDWARD R. |
分类号 |
H01P5/02 |
主分类号 |
H01P5/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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