SEMICONDUCTOR MEMORY MODULE WITH BUS ARCHITECTURE

摘要

A semiconductor memory module equipped with a bus architecture is provided to transfer signals output from a control chip to memory chips almost at the same time through different buses. The memory chips(U1-U8) and the control chip(SC) are arranged on a module circuit board(MP). The first bus(CLKB1) having the first and second terminal transfers the first control signal. The second bus(CLKB2) having the first terminal and at least two second terminals transfers the second control signal. The control chip accesses the first chips(U1-U2) or the second chips(U7-U8) at the same time for read/write access to the semiconductor memory module. The control chip is connected to the first terminal of the first bus and the memory chips are connected to the first bus along the first bus between the first and second terminal of the first bus. Each chip of the first chips is connected to the bus by neighboring to each chip of the second chips.