| 摘要 |
<p>The cell includes a bistable flip-flop realized by two cross-coupled inverters (INV1, INV2) for volatile storage of binary information. The binary information is stored in the form of potentials of memory nodes (K1, K2). A single binary programmable resistor (R1) secures the information stored in the flip-flop, during the transition into a power-down mode. Two switches (Sw3, Sw4) are provided for securing the binary information, where the switches serve for PC-reset operation and save-operation, respectively. Switches (Sw1, Sw2) are used for retrieving the binary information from the resistor. An independent claim is also included for a shift register including a non-volatile memory cell.</p> |
