| 摘要 |
A power up reset circuit of a semiconductor memory device is provided to prevent an operation error of an internal circuit, by using a stable power up reset signal. A first voltage detection part(100) provides a first power up reset signal by detecting a first voltage level of an internal power supply voltage, which increases during a power up period. A second voltage detection part(200) provides a second power up reset signal by detecting a second voltage level higher than the first voltage level of the internal power supply voltage. A pulse generation part(300) generates a reset pulse in response to the second power up reset signal. A control part(400) generates a third power up reset signal by receiving the first power up reset signal and the reset pulse. The third power up reset signal determines an initial logic level by an initial logic level of the first power up reset signal, and shifts the logic level in response to an initial reset pulse of the reset pulse.
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