摘要 |
<p>A clock data recovery loop that can be used over a wide range of data rates and maintain second-order behavior includes a nonlinear (e.g., Bang-Bang) phase detector (311), a charge pump (31), an RC loop filter (R,C), and signal generator (e.g., a voltage controlled oscillator (VCO)). At low data rates, the loop may be operated with the charge pump (31) and loop filter (R,C) with stable second-order behavior, with the resistor (R) of the loop filter (R,C) serving as a proportional path. A separate proportional path (312) is also provided that provides phase detector output directly to a control input of the VCO, while the resistor (R) of the loop filter (R,C) is also bypassed. As increasing data rates give rise to third-order effects, the separate proportional path (312) may be activated to maintain second-order behavior.</p> |