发明名称 Define via in dual damascene process
摘要 The invention includes a process for manufacturing an integrated circuit, comprising providing a substrate comprising a dielectric layer over a conductive material, depositing a hardmask over the dielectric layer, applying a first photoresist over the hardmask and photodefining a trench, etching the hard mask and partially etching the dielectric to form a trench having a bottom, stripping the photoresist, applying a second photoresist and photodefining a slit across the trench, selectively etching the dielectric from the bottom of the trench down to the underlying conductive material. Both the hardmask and the second photoresist are used as a mask. Later, a connection to the underlying metal is formed and integrated circuits made thereby.
申请公布号 US7160799(B2) 申请公布日期 2007.01.09
申请号 US20030603041 申请日期 2003.06.24
申请人 AGERE SYSTEMS INC. 发明人 LYTLE STEVEN ALAN;WOLF THOMAS MICHAEL;YEN ALLEN
分类号 H01L21/4763;H01L21/768;H01L23/528;H01L23/538 主分类号 H01L21/4763
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