| 摘要 |
A synchronous semiconductor memory device is provided to stabilize the operation of a memory circuit by stabilizing the relation between a sampling clock signal and a transfer clock signal. A synchronous semiconductor memory device includes a clock synchronization circuit(110), a latency circuit(250), and a latency control circuit(200). The clock synchronization circuit receives an external clock signal and generates a data output clock signal. The latency circuit stores a read signal in response to at least one sampling clock signal. The latency circuit receives the data output clock signal and sequentially generates plural clock control signals. The latency circuit generates plural transfer clock signals, which are synchronized with the clock control signals and provides a latency signal in response to the transfer clock signal, which is related to the sampling clock signal used for storing the read signal. The latency control circuit delays the clock control signals by the sum of an output delay time and a read command delay time and generates the sampling clock signals, which are synchronized with delayed clock control signals.
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