发明名称 FET BIAS CIRCUIT
摘要 A circuit for biasing a Field Effect Transistor (FET) is provided. The FET has a gate, a drain, and a source and the circuit comprises a current limiting resistor having a first end and a second end, the first end being connected to the gate; and a closed-loop control circuit connected to the second end, applying and controlling DC voltage to the second end, so that a gate bias voltage that is applied to the gate becomes equal to a reference voltage of a predetermined DC voltage.
申请公布号 CA2335220(C) 申请公布日期 2007.01.09
申请号 CA20012335220 申请日期 2001.02.12
申请人 JAPAN RADIO CO., LTD. 发明人 TAKAHASHI, TAKETO;HONDA, TAMAKI;SAKAMOTO, HIRONORI
分类号 G05F1/46;H03F1/30;H03F3/193 主分类号 G05F1/46
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