| 摘要 |
A 3-level non-volatile semiconductor memory device and a page buffer for the same are provided to reduce noise by using first and second even bit lines as shielding lines, when memory cells of first and second odd strings are selected. A memory array includes non-volatile memory cells. A page buffer(200) is coupled with the memory array through first and second common bit lines and configured to map one to three bit data to threshold voltage levels of a series of first and second memory cells. A row decoder controls the word line of a selected memory cell. The page buffer includes a switch(SW), a first latch block(LTBK1), a second latch block(LTBK2), a dumping block(DPBK), and an output block(OTBK). The switch couples the first common bit line with the second common bit line. The first latch block is connected to the first common bit line through a first sensing node and stores predetermined first latch data. The second latch block is connected to the second common bit line through a second sensing node and stores predetermined second latch data. The dumping block is configured to control the voltage level of the second sensing node according to the first latch data. The output block outputs the data corresponding to the second latch data to an inner data line.
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