| 摘要 |
An address control circuit of a semiconductor memory device is provided to efficiently prevent an operation error by maintaining a valid address by latching and decoding an address at the same timing during data write and read operations and then outputting the address to a read/write driving buffer. A read driver buffer amplifies data of a bit line sense amplifier according to a block selection signal and an input/output strobe signal and then outputs the data to a global input/output line. A write driver buffer outputs data applied from the global input/output line to the bit line sense amplifier according to a write enable signal and the block selection signal. An address control part(100) outputs a column selection signal to select the bit line sense amplifier by delaying a column selection control signal, and outputs the input/output strobe signal by delaying the column selection signal by each different time, and generates the block selection signal by decoding a valid address when the column selection control signal is enabled during data read/write operation.
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