| 摘要 |
A shift register is provided to prevent a pull-down transistor from being degraded by periodically charging/discharging a node, to which a gate terminal of the pull-down transistor is connected. A shift register includes plural cascaded stages, which sequentially output scan pulses. Each of the stages receives at least two clock pulses of different phases, and includes first to fifth switching elements(Tr1,Tr2,Tr3,Tr4,Tr5), a pull-up switching element(Tru), and a pull-down switching element(Trd). The first switching element charges a first node with a high voltage. The second switching element discharges the first node with a low voltage in response to the scan pulse from the next stage. The third switching element charges a second node with a first clock pulse. The fourth switching element discharges the second node to a second voltage in response to a second clock pulse. A fifth switching element discharges the second node to the second voltage. The pull-up switching element outputs the first clock pulse as the scan pulse, in response to the high voltage charged on the first node, and supplies the scan pulse to the gate line, the previous stage, and the next stage. The pull-down switching element supplies the low voltage to the gate line, the previous stage, and the next stage in response to the first clock pulse charged on the second node.
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