| 摘要 |
<p>A semiconductor device and its manufacturing method are provided to reduce a threshold swing value and a DIBL(Drain Induced Barrier Lowing) value and to improve current characteristics. A portion of a substrate is protruded to form a pin. A gate insulating layer is formed along an upper surface of the pin. A gate conductive layer(204) is formed on the gate insulating layer. The gate conductive layer crosses the pin. A charge activating layer(206) is formed on the resultant structure to cover the pin. Source/drain regions are formed by performing an ion implantation on the charge activating layer and the pin.</p> |
